EPFL Logic Synthesis Libraries
Collection of modular libraries for the development of logic synthesis applications
A suite of modular C++ libraries supporting logic synthesis research, including data structures for Boolean networks, And-Inverter Graphs (AIGs), and k-LUT networks, along with algorithms for technology mapping, rewriting, and simulation. Designed for composability and used as the foundation of the ABC-compatible EPFL synthesis flow.
Low-Level
- Research papers
- Technical
The Integrated Systems Laboratory studies design technologies for circuits and systems. The objective is to research the interplay of hardware and software design for traditional (computation on silicon) and non-traditional (nanotechnology and biosensors) systems.
This page was last edited on 2022-07-05.
This page was last edited on 2022-07-05.