HardCilk

HardCilk

Cilk-like task parallelism for FPGAs

HardCilk implements Cilk-style fork-join task parallelism directly in hardware for FPGAs, enabling dynamic task spawning and synchronization at the circuit level. It brings the expressive parallel programming model of Cilk to reconfigurable computing without a software runtime.

ConcurrencyHardwareLow-Level
Maturity
Support
C4DT
Inactive
Lab
Active

Processor Architecture Laboratory

Processor Architecture Laboratory
Paolo Ienne

Prof. Paolo Ienne

Excellent performance in computing systems is the result of a judicious blend of computer architecture, compiler technology, and hardware implementation. The choices in each of these areas must strongly depend on the technical possibilities offered in the others. We want to understand better how to exploit synergies across the above fields and we wish to pass this knowledge over to our students.

This page was last edited on 2026-04-02.