Bitfiltrator

Bitfiltrator

Bitfiltrator is an automated bitstream parameter extraction tool for Xilinx UltraScale and UltraScale+ FPGAs.

Prior work has reverse-engineered parts of the bitstream format for security or debugging/instrumentation activities, but no paper has explained how to do this reverse engineering systematically! Our work bridges this gap by explaining: (1) the various parameters needed to navigate a bitstream correctly, (2) the experiments to obtain them, and (3) the many pitfalls and erroneous assumptions to avoid while undertaking this endeavor. We demonstrate our technique by using it to extract the bitstream format of initial LUT equations, LUTRAM contents, BRAM contents, and register values in Xilinx UltraScale and UltraScale+ FPGAs. Our methods are implemented in an open-source tool, Bitfiltrator [1], that can extract device layouts and architecture-specific bitstream formats for these cells automatically and without physical access to an FPGA.

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Very Large Scale Computing Lab

Very Large Scale Computing Lab

Prof. James Larus

The Very Large Scale Computing Lab (VLSC) is trying to solve some of the critical software and hardware challenges of building large-scale services. These services may encompass tens of geo-distributed data centers, each of which can contain tens of thousands of servers. Compounded by challenges of scale and distribution, services also have very high availability and responsiveness requirements, and they are under continual development and evolution.

This page was last edited on 2023-03-22.